With advantages of high integration density, low cost and high reliability, FOPLP has been adopted for power management ICs in automotive applications, and continues to drive adoption in support of next generation radio frequency ICs for LEO satellites.
FOPLP technology enables coreless packaging that significantly reduces package thickness and achieves high-density circuit layouts. By employing a Redistribution Layer (RDL) to directly connect the chip to the substrate, it shortens signal transmission paths and—thanks to its coreless structure—reduces thermal resistance, enhancing heat dissipation efficiency while eliminating costly substrate materials. Moreover, by leveraging the high-throughput capabilities of large-area panels, FOPLP substantially lowers per-unit packaging costs, providing a flexible and efficient advanced-packaging solution for RFICs, PMICs, high-performance computing (HPC), AI, and other applications that demand stringent control over package thickness and thermal management.
In the Chip-First process, chips are attached to the carrier before the redistribution layer (RDL) is formed. This approach is well suited for smaller, simpler devices—such as PMICs and RF ICs.
In the Chip-Last process, chips are attached after the RDL structure has been completed. This method is ideal for higher-density, larger-chip applications, such as AI chips and high-performance computing (HPC) processors.
Panel-level packaging that supports both processes delivers optimal performance with high efficiency and low cost. This framework also enables the packaging industry to meet the diverse needs of heterogeneous integration and high-frequency, high-performance applications.
Thanks to our extensive technology portfolio, we can offer customized and highly efficient integrated manufacturing solutions for mass production. Our FOPLP RDL production solutions include the following building blocks and is suitable for various subtrates:
Comprehensive service package (from planning the equipment to the complete production system and after-sales services)
The new vertical electroplating system does not require a stencil, which saves the purchase costs for the stencil, the consumption of electroplating solution and the costs for the cleaning solution during the process.
In addition, the electroplating system has a modular design and can be configured flexibly depending on the customer's production capacity and operating area. The components can be operated and dismantled quickly, are easy to maintain and can help the customer to run an efficient production.
Chip-on-Panel-on-Substrate (CoPoS) boots system integration through panel-level packaging
